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[Archive] [M/T-Series]Explanation of the 'fpc_recv_power_cycle: FPC 4, power cycle duration 1000 msec' log message



Article ID: KB24386 KB Last Updated: 30 Jul 2020Version: 2.0
This article describes the issue of FPC going through a power cyle, with the fpc_recv_power_cycle: FPC 4, power cycle duration 1000 msec log message being generated.
  • The FPC power cycle of 1000 msec is due to an issue with the R chip SRAM on the FPC.

  • The R chip SRAM is used for SRAM read addresses and to compute the appropriate parameters, which are required by R chip, for the route/next-hop lookup.

  • Typically, if there is an error in the SRAM, the device will try to power cycle the FPC to clear the SRAM; so as to avoid the incorrect computation of these parameters.
The system scans all SRAMs to look for parity errors. This routine distinguishes two types of failures. The first type is a recoverable, single-bit error and is known as SER. The bad bit can be changed by a write; so the parity error can be corrected.

The second type of failure is a non-recoverable multi-bit error and is known as SEL. The bits may be spread over several words. The bad bits may be in a variety of states; but some of them will be latched up and cannot be changed by writing. The only way to fix this to power-cycle the FPC.

These two states are distinguished by counting the number of parity errors, which are encountered during the scan. If it is just one error, it is a SER. In that case, the word can be corrected from shadow memory. If there is more than one parity error, they are assumed as SEL and the RE is requested to power-cycle the FPC.
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