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[QFX] EX4600/QFX5100/QFX5200 interfaces are auto-channelized while connecting with QFX10K

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Article ID: KB32409 KB Last Updated: 13 Jul 2018Version: 2.0 Summary:

This article explains the behavior of auto-channelization on EX4600, QFX5100, and QFX5200 interfaces while connecting with QFX10000 and suggests a workaround for the same. 

 

Symptoms:

The hardware configuration and interface behavior is as follows:

QFX5100 hardware (40-GE SFP connected to the switch):

switch@JNPR-QFX> show chassis hardware
Hardware inventory:
Item             Version  Part number  Serial number     Description
Chassis                                ## xxxxxxx ##    QFX5100-24Q-2P
Pseudo CB 0
Routing Engine 0          BUILTIN      BUILTIN           QFX Routing Engine
FPC 0            REV 38   650-049942   ## xxxxxxx ##     QFX5100-24Q-2P
  CPU                     BUILTIN      BUILTIN           FPC CPU
  PIC 0                   BUILTIN      BUILTIN           24x 40G-QSFP
    Xcvr 18      REV 01   740-060378   ## xxxxxxx ##       QSFP+40GE-AOC-10M <<<<<
    Xcvr 19      REV 01   740-060378   ## xxxxxxx ##       QSFP+40GE-AOC-10M <<<<<
    Xcvr 20      REV 01   740-060378   ## xxxxxxx ##       QSFP+40GE-AOC-10M <<<<<

QFX5100 interface configuration:

switch@JNPR-QFX> show configuration | display set | match ae1
set interfaces et-0/0/18 ether-options 802.3ad ae1
set interfaces et-0/0/19 ether-options 802.3ad ae1
set interfaces et-0/0/20 ether-options 802.3ad ae1

Interfaces do not show up after connecting the EX4600/QFX5100/QFX5200 Series of switches to the QFX10K switch:

switch@JNPR-QFX> show interfaces et-0/0/18
error: device et-0/0/18 not found
 
{master:0}
switch@JNPR-QFX> show interfaces et-0/0/19
error: device et-0/0/19 not found
 
{master:0}
switch@JNPR-QFX> show interfaces et-0/0/20
error: device et-0/0/20 not found
 
 
switch@QFX10K> show interfaces descriptions | match spoptk01
et-0/0/18                  Dest peer: Spine-1-et-0/0/16
et-0/0/19                  Dest peer: Spine-1-et-0/0/17
et-0/0/20                  Dest peer: Spine-1-et-0/0/18
ae1             up    down All to Spine-1
 
 
userA@JNPR-QFX> show interfaces statistics ae1
Physical interface: ae1, Enabled, Physical link is Down 
  Interface index: 776, SNMP ifIndex: 678
  Description: All to Spine-1
  Link-level type: Ethernet, MTU: 9192, Speed: Unspecified, BPDU Error: None, Ethernet-Switching Error: None, MAC-REWRITE Error: None, Loopback: Disabled,
  Source filtering: Disabled, Flow control: Disabled, Minimum links needed: 1, Minimum bandwidth needed: 1bps
  Device flags   : Present Running
  Interface flags: Hardware-Down SNMP-Traps Internal: 0x4000
  Current address: c8:e7:f0:38:b2:aa, Hardware address: c8:e7:f0:38:b2:aa
  Last flapped   : 2017-12-15 17:34:27 CET (3d 16:37 ago)
  Statistics last cleared: Never
  Input rate     : 0 bps (0 pps)
  Output rate    : 0 bps (0 pps)
  Input errors: 0, Output errors: 0

Interfaces get auto-channelized and converted into xe- ports:

{master:0}[edit]
userA@QFX10K# run show interfaces terse | match "xe-|18:|19:|20:"
xe-0/0/18:0             up    up
xe-0/0/18:1             up    up
xe-0/0/18:2             up    up
xe-0/0/18:3             up    up
xe-0/0/19:0             up    up
xe-0/0/19:1             up    up
xe-0/0/19:2             up    up
xe-0/0/19:3             up    up
xe-0/0/20:0             up    up
xe-0/0/20:1             up    up
xe-0/0/20:2             up    up
xe-0/0/20:3             up    up

From chassisd traces, the following messages are reported in the chassisd logs:

Dec 15 17:34:21  auto-chan: sending the global auto-channelization 0 flag to pfe  <<<---
Dec 15 17:34:21 CHASSISD_PARSE_COMPLETE: Using new configuration
Dec 15 17:34:53  got lldp req poe info msg from lldpd intf:et-0/0/18.32767
Dec 15 17:35:29  pic_update_port_range Deleting IFD: et-0/0/18
Dec 15 17:35:29  ifdev_detach_port(et-0/0/18)
Dec 15 17:35:29  ifd et-0/0/18 marked as gone
Dec 15 17:35:29  PIC (fpc 0 pic 0) message operation: change. ifd count 53, flags 0x3 in mesg
Dec 15 17:35:29  pic_update_port_range Deleting IFD: et-0/0/19
Dec 15 17:35:29  ifdev_detach_port(et-0/0/19)
Dec 15 17:35:29  ifd et-0/0/19 marked as gone
Dec 15 17:35:29  PIC (fpc 0 pic 0) message operation: change. ifd count 52, flags 0x3 in mesg
Dec 15 17:35:29  pic_update_port_range Deleting IFD: et-0/0/20
Dec 15 17:35:29  ifdev_detach_port(et-0/0/20)
Dec 15 17:35:29  ifd et-0/0/20 marked as gone
Dec 15 17:35:29  PIC (fpc 0 pic 0) message operation: change. ifd count 51, flags 0x3 in mesg
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM422700Y    
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM422600E    
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 18, speed 10000000000                 <<<---
Dec 15 17:35:32  xe-0/0/18:0 ifm_channel: 0x0, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/18:0, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/18:0
Dec 15 17:35:32  xe-0/0/18:0: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:0 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:0 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 18, speed 10000000000                 <<<---
Dec 15 17:35:32  xe-0/0/18:1 ifm_channel: 0x1, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/18:1, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/18:1
Dec 15 17:35:32  xe-0/0/18:1: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:1 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:1 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 18, speed 10000000000
Dec 15 17:35:32  xe-0/0/18:2 ifm_channel: 0x2, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/18:2, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/18:2
Dec 15 17:35:32  xe-0/0/18:2: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:2 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:2 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 18, speed 10000000000
Dec 15 17:35:32  xe-0/0/18:3 ifm_channel: 0x3, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:73
Dec 15 17:35:32  capability: xe-0/0/18:3, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/18:3
Dec 15 17:35:32  xe-0/0/18:3: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:3 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/18:3 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 19, speed 10000000000
Dec 15 17:35:32  xe-0/0/19:0 ifm_channel: 0x0, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:77
Dec 15 17:35:32  capability: xe-0/0/19:0, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/19:0
Dec 15 17:35:32  xe-0/0/19:0: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:0 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:0 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 19, speed 10000000000
Dec 15 17:35:32  xe-0/0/19:1 ifm_channel: 0x1, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:77
Dec 15 17:35:32  capability: xe-0/0/19:1, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/19:1
Dec 15 17:35:32  xe-0/0/19:1: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:1 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:1 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 19, speed 10000000000
Dec 15 17:35:32  xe-0/0/19:2 ifm_channel: 0x2, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:77
Dec 15 17:35:32  capability: xe-0/0/19:2, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/19:2
Dec 15 17:35:32  xe-0/0/19:2: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:2 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:2 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 19, speed 10000000000
Dec 15 17:35:32  xe-0/0/19:3 ifm_channel: 0x3, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:77
Dec 15 17:35:32  capability: xe-0/0/19:3, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/19:3
Dec 15 17:35:32  xe-0/0/19:3: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:3 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/19:3 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM422700Y    
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM422600E    
Dec 15 17:35:32  pic_copy_port_info:Got SFP Rev=REV 01, Pno=740-060378, Sno=1FCM4227001    
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 20, speed 10000000000
Dec 15 17:35:32  xe-0/0/20:0 ifm_channel: 0x0, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:81
Dec 15 17:35:32  capability: xe-0/0/20:0, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/20:0
Dec 15 17:35:32  xe-0/0/20:0: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:0 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:0 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 20, speed 10000000000
Dec 15 17:35:32  xe-0/0/20:1 ifm_channel: 0x1, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:81
Dec 15 17:35:32  capability: xe-0/0/20:1, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/20:1
Dec 15 17:35:32  xe-0/0/20:1: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:1 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:1 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 20, speed 10000000000
Dec 15 17:35:32  xe-0/0/20:2 ifm_channel: 0x2, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:81
Dec 15 17:35:32  capability: xe-0/0/20:2, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/20:2
Dec 15 17:35:32  xe-0/0/20:2: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:2 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:2 IFM type is Ether, SyncE TLV is added
Dec 15 17:35:32  create_pic_entry: pic i2c 0xf0ac, hw qs 12 supported qs 12, flags 0x0, pic port 20, speed 10000000000
Dec 15 17:35:32  xe-0/0/20:3 ifm_channel: 0x3, ifm_fe = 0, local_dev_id:0, global_dev_id:0, port_num:81
Dec 15 17:35:32  capability: xe-0/0/20:3, cap flag = 43072, media: 2 porttype 27
Dec 15 17:35:32  ifdev_create entered xe-0/0/20:3
Dec 15 17:35:32  xe-0/0/20:3: large delay buffer cleared
Dec 15 17:35:32  fpc_is_synce_cap: FPC i2c: 0xbce, PIC type: 0xf0ac
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:3 Not SyncE capable
Dec 15 17:35:32  pic_update_ifdev_tlvs: xe-0/0/20:3 IFM type is Ether, SyncE TLV is added

 

Solution:

As documented in Channelizing Interfaces, by default, the 40-Gbps QSFP+ ports on the EX4600, QFX5100, and QFX5200 Series of switches are channelized automatically (auto-channelized) if any of the four channels on the 40-Gbps QSFP+ port receive data, unless channelization is configured either at the chassis level or at the port level.

Note: If you are using the EX4600, QFX5100, or QFX5200 switch with a peer QFX10000 switch, you must disable auto-channelization on the EX4600, QFX5100, or QFX5200 switch.

You can disable auto-channelization by including the “disable-auto-speed-detection” statement:

[edit chassis fpc slot-number pic pic-number (port port-number | port-range port-range-low port-range-high) channel-speed] disable-auto-speed-detection

For example:

  • user@switch# set chassis fpc 0 pic 0 port 2 channel-speed disable-auto-speed-detection

or

  • user@switch# set chassis fpc 0 pic 0 port-range 2 4 channel-speed disable-auto-speed-detection

 

Modification History:

2018-07-13: Added the QFX5200 Series of switches to the article; other minor modifications made (non-technical)

 

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