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Understanding Physical Coding Sublayer (PCS) errors, Bit errors (BER) and Errored Blocks

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Article ID: KB33921 KB Last Updated: 05 Mar 2019Version: 1.0
Summary:

This article explains Physical Coding Sublayer (PCS) errors and the possible causes.

Symptoms:

PCS errors may be seen on the interface and cause the link to flap on and off. In this example, Bit errors are seen as well as some Errored blocks​.

{master:0}
root@c04-36> show interfaces xe-0/0/3
Physical interface: xe-0/0/3, Enabled, Physical link is Up
  Interface index: 650, SNMP ifIndex: 568
  Description: xe-0/0/3 on FPC0-QFX5100-96S-8Q-r012 to xe-1/0/3 on FPC1-jtac-QFX5100-96S-8Q-r011
  Link-level type: Ethernet, MTU: 1514, LAN-PHY mode, Speed: 10Gbps,
  BPDU Error: None, Loop Detect PDU Error: None, Ethernet-Switching Error: None,
  Source filtering: Disabled
  Ethernet-Switching Error: None, MAC-REWRITE Error: None, Loopback: Disabled,
  Flow control: Disabled, Media type: Fiber
  Device flags   : Present Running
  Interface flags: SNMP-Traps Internal: 0x4000
  Link flags     : None
  CoS queues     : 12 supported, 12 maximum usable queues
  Current address: 44:f4:77:fa:45:c6, Hardware address: 44:f4:77:fa:45:c6
  Last flapped   : 2019-02-04 23:05:20 PST (3d 07:57 ago)

    Input rate     : 341584 bps (418 pps)
  Output rate    : 341584 bps (418 pps)​
  Active alarms  : None
  Active defects : None
  PCS statistics                      Seconds
    Bit errors                             17
    Errored blocks                         39

  Ethernet FEC statistics              Errors
    FEC Corrected Errors                    0
    FEC Uncorrected Errors                  0
    FEC Corrected Errors Rate               0
    FEC Uncorrected Errors Rate             0
  PRBS Statistics : Disabled
  Interface transmit statistics: Disabled
Cause:

Bit errors occur at random intervals due to various reasons which can be counted as PCS Errors. Typically, the PCS errors are attributed to physical processing elements, such as fiber / patch panels / ODF / CFP optics. It should be noted that 100GE end-to-end performance is much more sensitive to optical path cleanliness than 10GE due to the inner workings of 100GE technology. PCS errors are also seen when there is a link transition event due to fiber pull / PIC offline or online events. During link down/up transitions, it is expected to see PCS errors increase for a short period of time; this is due to initial synchronization / validation of the two Ethernet end points. PCS errors are always counted from the incoming direction at the receiving node.

The Physical Coding Sublayer (PCS) Errored blocks and bit errors are usually caused by the physical layer with either bad Fiber or bad XFP. In some instances, the same behavior is seen when the Optics RX power is low on the Receiver side. In this case, we need to check both the physical medium as well as the port on the local device. 

Solution:

The PCS function is based on 64B/66B coding mechanism. All 10/40/100Gb Ethernet Frame is chopped into 64 bits of data by the PCS component. The PCS component prepends a 2 bit (called sync bits) to this 64 bit of data, making it a total of 66 bit (also known as Blocks) before distributing these blocks of data into PCS LANE.

  • Data Block SYNC-Bit should always be set to “01”

  • Control Block SYNC-Bit should always be set to “10”

  • “11” or “00” found in sync header is a “BER” error

  • Once we find a single Bit error under the Sync header, the PCS Converts following block to an errored block

  • When one of the 2 Sync header bit is incorrect, its classified as Bit and Block error

  • When both the 2 bits on a Sync header is incorrect(its treated as an illegal pattern) and classified as Block Error only, there is no bit error on this condition

  • When the 2 Sync header bits are correct, but if the Block type is incorrect on the control block(illegal control code), its also classified as Block-error

The show interfaces <xe/et-x/x/x> CLI command displays PCS fault conditions. The definitions of the counters are as follows:

Bit errors - The number of seconds during which at least one bit error rate (BER) occurred while the PCS receiver is operating in normal mode.
Errored blocks - The number of seconds when at least one errored block occurred while the PCS receiver is operating in normal mode.

When PCS errors occur, check the physical connections between the two end points which includes fiber, patch panels, Optical Distribution Frame (ODF), C Form-factor Pluggable (CFP) optics.

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