This article describes FPGA (Field Programmable Gate Array) upgrade behavior of SRX1400 after replacing SPC and Junos upgrade in a dual SPC scenario.

On SRX1400, the FPGA version of SPC corresponds with Junos version and it is automatically upgraded when FPGA version is mismatched with Junos version.

In dual SPC scenario, when SPC slot2 FPGA upgrade is run, FPC0 will go offline and raise failure alarm.

SPC FPGA upgrade may occur in the following situation:

• Junos upgrade from old Junos (e.g 12.1X46) to 12.3X48 release
• Replacing SPC with SPC has old FPGA version
• SRX1400 with Dual SPC, FPGA upgrade will run when SPC on SRX1400 slot2 is replaced with SPC installed on SRX3K 

After SPC2 FPGA upgrade is run, SRX1400 raises FPC0 alarm because FPC0 is offline.

root> show chassis alarms no-forwarding

2 alarms currently active
Alarm time               Class  Description
2019-01-01 00:00:00 UTC  Major  FPC 0 Major Errors
2019-01-01 00:00:00 UTC  Major  FPC 0 PIC 0 Failure

FPC0 status can be confirmed with the following command:

root> show chassis fpc pic-status
Slot 0   Online       SRX1k 10GE SYSIO
  PIC 0  Offline      6x 1GE RJ45 3x 1GE SFP 3x 10GE SFP+
Slot 1   Online       SRX1k Dual Wide NPC+SPC Support Card
  PIC 0  Online       SPU Flow
Slot 2   Online       SRX3k SPC
  PIC 0  Online       SPU Cp-Flow
Slot 3   Online       BUILTIN NPC
  PIC 0  Online       NPC PIC

In the syslog message, following is seen for FPGA upgrade:

Jan  1 00:00:00 node0.cpp0 Version of swanhill fpga in slot 2 is mismatch, expected 1100010, but current is 102007c
Jan  1 00:00:00 node0.cpp0 Version of Main FPGA in slot 2 is mismatch.
Jan  1 00:00:00 node0.cpp0 Upgrade spc2 main FPGA image ...

This behavior is designed specific in SPC slot2 on SRX1400.

When FPC0 alarm is raised after Junos upgrade or SPC replacement, take following actions:

• Junos-Upgrade:

  Run the command, 'request system reboot' to reboot the device.

• Replacement:

  Run command, 'request system reboot' to reboot the device.

  As a precaution, install spare SPC to spare chassis with the same Junos version as the device in production to upgrade SPC FPGA version before replacement.