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[QFX] Understanding Port Channelization Mapping in QFX10000-30C and QFX10000-60C

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Article ID: KB35849 KB Last Updated: 05 Jun 2020Version: 1.0
Summary:

The line cards in QFX10000 modular switches combine a Packet Forwarding Engine (PFE) and Ethernet interfaces in a single assembly. Line cards are field-replaceable units (FRUs) that can be installed in the line card slots at the front of the switch chassis. 

Channelized interfaces enable you to configure a number of individual channels that subdivide the bandwidth of a larger interface and minimize the number of Physical Interface Cards (PICs) that installation requires.

This article explains in detail how the ports on QFX10000-30C and QFX10000-60C switch variants are made available and disabled while considering channelization. The article also describes the "fifth port disabled" concept in some detail.

 

Solution:

Beginning with Junos OS Release 17.1R1, 40-Gigabit Ethernet ports on the QFX10000-30C line card can be channelized to 10-Gigabit Ethernet. The QFX10000-30C and QFX10000-60C line cards do not have port groups; instead, port behavior is tied to the ASIC that is associated with the port. Therefore, you must configure each port individually in order to channelize a 40-Gigabit Ethernet port to four independent 10-Gigabit Ethernet ports using copper or fiber breakout cables.

Further, when these ports are in channelization mode, every fifth port is disabled. Let's consider the following table to understand how the actual ports are marked as "available" or "disabled" for channelization.

Port Mapping: QFX10000-30C
       ASIC                

Physical Ports available for Channelization

Physical Ports that become disabled
PE0 0,2,4,8 6
PE1 10,12,14,18 16
PE2 20,22,24,28 26
PE3 1,3,5,9 7
PE4 11,13,15,19 17
PE5 21,23,25,29 27

Representing the Port Alignment on the device (QFX10000-30C) for better understanding:

0      2      4       6      8      10      12      14      16      18     20     22      24     26     28
1      3      5       7      9      11      13      15      17      19     21     23      25     27     29

You can see that ports are numbered as (0,1) in one column, (2,3) in the second column, (4,5) in the third column, and so on. As per the current design in QFX10000-30C and QFX10000-60C, the fifth port remains disabled. The underlined ports in the table above are the fifth ports that are disabled.

Now when you consider each row in the above Port Alignment representation, except for the first set wherein the fourth port appears to be disabled, you will see that every fifth port is disabled. This becomes clearer when you imagine the above rows as a loop: 28,0,2,4 are available and 6, being the fifth port, is therefore disabled. In the second row, similarly 7 becomes the disabled fifth port, whereas 29,1,3,5 are available.

Example

Row 1:    28,0,2,4 are available and 6 is disabled
Row 2:    29,1,3,5 are available and 7 is disabled
Row 1:    8,10,12,14 are available and 16 is disabled.
Row 2:    9,11,13,15 are available and 17 is disabled
Row 1:    18,20,22,24 are available and 26 is disabled
Row 2:    19,21,23,25 are available and 27 is disabled

If you want to continue with the next port, you start again with 28 in Row 1 and 29 in Row 2. When you apply the fifth port disabled design, you get the first combination again: 28,0,2,4 are available and 6 is disabled (Row 1) and 29,1,3,5 are available and 7 is disabled (Row 2).

Note: Row here refers to a horizontal line from left to right and column refers to the vertical line from top to bottom.

The same rule applies to Port Mapping on QFX10000 60C as well.

Port Mapping: QFX10000-60C
       ASIC                 

Physical Ports available for Channelization

Physical Ports that become disabled
PE0 30,32,34,38 36
PE1 31,33,35,39 37
PE2 40,42,44,48 46
PE3 41,43,45,49 47
PE4 50,52,54,58 56
PE5 51,53,55,59 57
PE6 0,2,4,8 6
PE7 1,3,5,9 7
PE8 10,12,14,18 16
PE9 11,13,15,19 17
PE10 20,22,24,28 26
PE11 21,23,25,29 27
 

For QFX10000-60C port representation, refer to Port Mapping for QFX10000 60C.

 

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